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Rev 1; 9/07
10MHz to 51.84MHz TCXO
General Description
The DS4026 is a temperature-compensated crystal oscillator (TCXO) that provides 1ppm frequency stability over the -40C to +85C industrial temperature range. Each device is factory calibrated over temperature to achieve the 1ppm frequency stability. Standard frequencies for the device include 12.8, 19.44, 20.0, 38.88, 40.0, and 51.84MHz. Contact the factory for custom frequencies. The DS4026 provides excellent phase-noise characteristics. The output is a push-pull CMOS square wave with symmetrical rise and fall times. In addition, the DS4026 is designed to provide a maximum frequency deviation of less than 4.6ppm over 10 years. The device also provides an I2C interface to allow pushing and pulling of the output frequency by a minimum of 8ppm (5ppm for 10MHz) with typical 1ppb resolution. The DS4026 implements a temperature-to-voltage conversion with a nonlinear relationship. The output from the temperature-to-voltage converter is used to drive the voltage-controlled crystal oscillator to compensate for frequency change. The device implements an on-chip temperature sensor lookup table, and a digital-to-analog converter (DAC) to adjust the frequency. An I2C interface used to communicate with the DS4026 performs temperature readings and frequency push-pull.
Features
o 1ppm Frequency Accuracy Over -40C to +85C o Standard Frequencies: 12.8, 19.44, 20.0, 38.88, 40.0, 51.84MHz o Maximum 4.6ppm Deviation Over 10 Years o Minimum 8ppm (5ppm for 10MHz) Digital Frequency Tuning Through I2C Interface o Surface-Mount 16-Pin SO Package o Pb Free/RoHS Compliant
DS4026
Pin Configuration
TOP VIEW
GNDA 1 VREF 2 VCC 3 VOSC 4 GNDOSC 5 N.C. 6 N.C. 7 N.C. 8 16 VCCD 15 FOUT 14 GNDD 13 SCL
DS4026
12 SDA 11 GND 10 N.C. 9 N.C.
Applications
Reference Clock Generation Telecom/Datacom/SATCOM Wireless Test and Measurement
SO
Ordering Information
PART DS4026S+BCC DS4026S+BCN DS4026S+HCC DS4026S+HCN DS4026S+JCC DS4026S+JCN TEMP RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C OUTPUT (fNOM) (MHz, CMOS) 12.8 12.8 19.44 19.44 20.0 20.0 PIN-PACKAGE 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO TOP MARK* DS4026-BCC DS4026-BCN DS4026-HCC DS4026-HCN DS4026-JCC DS4026-JCN
Ordering Information continued at end of data sheet.
+Denotes a lead-free package. *The top mark will include a "+" for a lead-free/RoHS-compliant device.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10MHz to 51.84MHz TCXO DS4026
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC, VCCD, and VOSC Relative to Ground..............................................-0.3V to +3.8V Voltage Range on SDA, SCL, and FOUT Relative to Ground...................................-0.3V to (VCC + 0.3V) Operating Temperature Range (noncondensing)....-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature...............................See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C, unless otherwise noted.)
PARAMETER Power-Supply Voltage Oscillator Power Supply Driver Power Supply SYMBOL VCC VOSC VCCD CONDITIONS MIN 3.135 3.135 3.135 TYP 3.3 3.3 3.3 MAX 3.465 3.465 3.465 UNITS V V V
DC ELECTRICAL CHARACTERISTICS (Note 1)
(VCC = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise noted.) (Notes 2, 3)
PARAMETER VCC Active-Supply Current VOSC Oscillator Active-Supply Current SYMBOL ICC (Note 4) FOUT CMOS output on, CL = 10pF, frequency < 25MHz IOSC FOUT CMOS output on, CL = 10pF, frequency 25MHz FOUT CMOS output on, CL = 10pF, frequency < 25MHz ICCD FOUT CMOS output on, CL = 10pF, frequency 25MHz -1 Output off -1 0.7 x VCC -0.3 VCC = 3.0V, VOL = 0.4V VCCD = 3V, IOH = -2mA VCCD = 3V, IOL = 2.0mA (0.1 x VCCD) - (0.9 x VCCD) 0.5 x VCCD (Note 5) 45 2 55 2.4 0.4 CONDITIONS MIN TYP 1.5 3 5 2 3 MAX 2.5 4 mA 9 3 mA 5 +1 +1 VCC + 0.3 +0.3 x VCC 3 A A V V mA V V ns % UNITS mA
VCCD Driver Active-Supply Current SCL Input Leakage SDA Leakage SCL, SDA High Input Voltage SCL, SDA Low Input Voltage SDA Logic 0 Output FOUT High Output Voltage FOUT Low Output Voltage FOUT Rise/Fall Time FOUT Duty Cycle
ILI ILO VIH VIL IOL VOH VOL tR/tF tD
2
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10MHz to 51.84MHz TCXO
AC ELECTRICAL CHARACTERISTICS (Note 1)
(VCC = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER Frequency Stability vs. Temperature Frequency Stability vs. Voltage Aging, First Year Aging, Years 2-15 Frequency Pull Range Except 10MHz 10MHz SYMBOL f1/TA f1/V f1/Yr f1/Yr f fRES CONDITIONS CL = 10pF to ground CL = 10pF to ground, +25C (Note 5) (Note 5) FTUNEH = 3Fh and FTUNEL = FFh; FTUNEH = 40h and FTUNEL = 00h at +25C MIN fNOM - 1ppm -2 -1 -2 8 5 15 10 1 TYP fNOM MAX fNOM + 1ppm +2 +1 +2 UNITS ppm ppm/V ppm ppm ppm ppb
DS4026
Frequency Pull Resolution
PHASE NOISE
PHASE NOISE (dBc/Hz) (TYPICAL, +25C, 3.3V) OFFSET (MHz) 12.80 19.44 20.00 CARRIER FREQUENCY 38.88 40.00 51.84 10.0 16.384 16.8 24.0 10Hz -88.41 -82.63 -83.71 -79.01 -80.80 -74.09 -92.52 -87.44 -89.6 -83.98 100Hz -130.16 -125.12 -120.76 -120.06 -115.44 -120.39 -134.83 -128.53 -126.20 -119.45 1kHz -147.84 -145.03 -145.44 -141.75 -141.17 -142.33 -147.22 -147.67 -146.88 -143.08 10kHz -150.84 -146.87 -150.96 -150.59 -151.59 -151.14 -150.84 -150.78 -151.90 -150.33 100kHz -151.71 -151.69 -151.18 -152.50 -152.37 -153.21 -151.25 -152.72 -152.28 -150.34 1MHz -151.87 -151.52 -151.45 -153.06 -153.00 -153.94 -150.84 -151.75 -151.93 -150.67
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10MHz to 51.84MHz TCXO DS4026
TEMPERATURE SENSOR ELECTRICAL CHARACTERISTICS (Note 1)
(VCC = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER Temperature Sensor Accuracy Temperature Sensor Conversion Time Temperature Sensor Resolution SYMBOL T tCONVT N2 CONDITIONS MIN -3 TYP MAX +3 11 12 UNITS C ms Bits
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition (Note 6) Low Period of SCL Clock High Period of SCL Clock Data Hold Time (Notes 7, 8) Data Setup Time (Note 9) Start Setup Time Rise Time of Both SDA and SCL Signals (Note 10) Fall Time of Both SDA and SCL Signals (Note 10) SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode CONDITIONS Standard mode MIN 0 100 4.7 1.3 4.0 0.6 4.7 1.3 4.0 0.6 0 0 250 100 4.7 0.6 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 1000 300 300 300 0.9 0.9 TYP MAX 100 400 UNITS kHz s s s s s ns s ns ns
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10MHz to 51.84MHz TCXO
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER Setup Time for STOP Condition Pin Capacitance SDA, SCL (Note 5) Capacitive Load for Each Bus Line (Note 10) Pulse Width of Spikes That Must Be Suppressed by the Input Filter SYMBOL tSU:STO CI/O CB tSP Fast mode 30 Fast mode CONDITIONS Standard mode MIN 4.7 0.6 10 400 TYP MAX UNITS s pF pF ns
DS4026
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
Typical values are at +25C, nominal supply voltages, unless otherwise indicated. Voltages referenced to ground. Limits at -40C are guaranteed by design and not production tested. Specified with I2C bus inactive. Guaranteed by design and not production tested. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 8: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 9: A fast-mode device can be used in a standard-mode system, but the requirement that tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does not stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 10: CB--total capacitance of one bus line in pF.
Data Transfer on I2C Serial Bus
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
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10MHz to 51.84MHz TCXO DS4026
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
ACTIVE-SUPPLY CURRENT vs. POWER-SUPPLY CURRENT
1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3.0 3.1 3.2
DS4026 toc01
ACTIVE-SUPPLY CURRENT vs. OSCILLATOR POWER SUPPLY
DS4026 toc02
ACTIVE-SUPPLY CURRENT vs. DRIVER POWER SUPPLY
10.0 51.84 8.0 CURRENT (mA)
DS4026 toc03
5.0 4.5 4.0 3.5 CURRENT (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0 12.8 51.84
12.8
51.84
CURRENT (mA)
6.0
4.0 12.8 2.0 -0.1
3.3 VCC (V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3 VOSC (V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3 VCCD (V)
3.4
3.5
3.6
FREQUENCY vs. FTUNE
DS4026 toc04
FREQUENCY vs. TEMPERATURE
20 18 15 13 10 8 5 3 0 -3 -5 -8 -10 -13 -15 -40 -20 0
DS4026 toc05
PHASE NOISE (TYP)
-5.0 -30.0 PHASE NOISE (dBc/Hz) -55.0 -80.0 -105.0 -130.0 12.8MHz -155.0 -180.0 51.84MHz 19.44MHz
DS4026 toc06
20 15 10 5 OFFSET (ppm) 0 -5 -10 -15 -20 -25 -30 4000h 000h VC (V) 3FFFh 12.8 51.84
DCOMP = 1
DEVIATION (ppm)
DCOMP = 0
38.88MHz
20
40
60
80
10
100
1000
10,000 100,000 1,000,000
TEMPERATURE (C)
OFFSET (Hz)
6
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10MHz to 51.84MHz TCXO
Pin Description
PIN 1 2 3 4 5 6-10 11 12 13 14 15 16 NAME GNDA VREF VCC VOSC GNDOSC N.C. GND SDA SCL GNDD FOUT VCCD Ground for DAC Voltage Reference Output. This pin must be decoupled with a 100F ceramic capacitor to ground. Power Supply for Digital Control and Temperature Sensor. This pin must be decoupled with a 100nF capacitor to ground. Power Supply for Oscillator Circuit. This pin must be decoupled with a 0.1F capacitor to ground. Ground for Oscillator Circuit No Connection. Must be connected to ground. Ground for Digital Control, Temperature Sensor, and Controller Substrate Serial Data Input/Output. SDA is the data input/output for the I C interface. This open-drain pin requires an external pullup resistor. Serial Clock Input. SCL is the clock input for the I C Interface and is used to synchronize data movement on the serial interface. Ground for Oscillator Output Driver Frequency Output, CMOS Push-Pull Power Supply for Oscillator Output Driver. This pin must be decoupled with a 0.1F capacitor to ground. A 20 resistor must be placed in series between the power supply and VCCD.
2 2
DS4026
FUNCTION
20 GNDA 100F 5% CERAMIC VREF VCCD FOUT GNDD 0.1F
DS4026
VCC 0.1F VOSC 0.1F GNDOSC N.C. N.C. N.C. GND N.C. N.C. SDA SCL
Figure 1. Typical Operating Circuit
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10MHz to 51.84MHz TCXO DS4026
VCC VCC TEMP SENSOR EEPROM ARRAY
A/D
GND VCC SCL SDA VCC
GND VREF
I2C INTERFACE
CONTROLLER
DAC
DS4026
GNDA
GND
GND
VCCD
VOSC CMOS BUFFER FOUT
GNDOSC
GNDD
Figure 2. Functional Diagram
Detailed Description
The DS4026 is a TCXO capable of operating at 3.3V 5%, and it allows digital tuning of the fundamental frequency. The device is calibrated in the factory to achieve an accuracy of 1ppm over the industrial temperature range, and its minimum pullability is 8ppm with a typical resolution of 1ppb (typ) per LSB. The DS4026 contains the following blocks: * Oscillator block with variable capacitor for compensation * Output driver block * Temperature sensor
* Controller to read the temperature, control lookup table, and adjust the DAC input * DAC output to adjust the capacitive load * I2C interface to communicate with the chip The oscillator block consists of an amplifier and variable capacitor in a Pierce crystal oscillator with a crystal resonator of fundamental mode. The oscillator amplifier is a single transistor amplifier and its transconductance is temperature compensated. The variable capacitor is adjusted by the DAC to provide temperature compensation. With the FTUNEH and FTUNEL registers, a minimum pullability of 8ppm (5ppm for 10MHz) is achieved with a typical resolution of 1ppb (typ) per LSB.
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10MHz to 51.84MHz TCXO
The output driver is a CMOS square-wave output with symmetrical rise and fall time. The temperature sensor provides a 12-bit temperature reading with a resolution of 0.0625C. The sensor is in continuous conversion mode. If DCOMP is set, conversions continue but temperature updates are inhibited. The controller coordinates the conversion of temperature into digital codes. When the temperature reading is different from the previous one or the frequency tuning register is changed, the controller looks up the two corresponding capacitance trim codes from the lookup table at a 0.5C increment. The trim codes are interpolated to 0.0625C resolution. The result is added with the tuning value from the frequency tuning register and loaded into the DAC registers to adjust voltage output. The monotonic DAC provides an analog voltage based on temperature compensation to drive the variable capacitor. The DS4026 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed.
Address Map
Disable Compensation Update (DCOMP)
DCOMP is bit 7 of the frequency tuning register (see the Frequency Tuning Register (00h-01h), POR = 00h table). When set to logic 1, this bit's temperature-compensation function is disabled. This disabling prevents the variable capacitor in the oscillator block from changing. However, the temperature register still performs temperature conversions. The temperature trim code from the last temperature conversion before DCOMP is enabled is used for temperature compensation. The FTUNE registers are still functional when DCOMP is disabled. The frequency tuning registers adjust the base frequency. The frequency tuning value is represented in two's complement data. Bit 6 of FTUNEH is the sign, bit 5 is the MSB, and bit 0 of FTUNEL is the LSB (see Table 1). When the tuning register low (01h) is programmed with a value, the next temperature update cycle sums the programmed value with the factory compensated value. This allows the user to digitally control the base frequency using the I2C protocol. These frequency tuning register bits allow the tuning of the base frequency. Each bit typically represents about 1ppb (typ). For FTUNEH = 3Fh and FTUNEL = FFh, the device pushes the base frequency by approximately +15ppm.
DS4026
Frequency Tuning Register (00h-01h), POR = 00h
ADDRESS 00h POR 01h POR BIT 7 DCOMP 0 Data 0 BIT 6 Sign 0 Data 0 BIT 5 Data 0 Data 0 BIT 4 Data 0 Data 0 BIT 3 Data 0 Data 0 BIT 2 Data 0 Data 0 BIT 1 Data 0 Data 0 BIT 0 Data 0 Data 0
Temperature Register (02h-03h)
ADDRESS 02h POR 03h POR BIT 7 Sign 0 Data 0 BIT 6 Data 0 Data 0 BIT 5 Data 0 Data 0 BIT 4 Data 0 Data 0 BIT 3 Data 0 0 0 BIT 2 Data 0 0 0 BIT 1 Data 0 0 0 BIT 0 Data 0 0 0
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10MHz to 51.84MHz TCXO DS4026
Table 1. Register Map
ADDRESS 00 01 02 03 SIGN BIT 7 DCOMP BIT 6 SIGN BIT 5 BIT 4 BIT 3 FTUNEH FTUNEL TREGH TREGL BIT 2 BIT 1 BIT 0 FUNCTION Frequency Tuning High Frequency Tuning Low Temperature MSB Temperature LSB
Read Mode
In the temperature register (see the Temperature Register (02h-03h) table), temperature is represented as a 12-bit code and is accessible at location 02h and 03h. The upper 8 bits are at location 02h and the lower 4 bits are in the upper nibble of the byte at location 03h. Upon power reset, the registers are set to a +25C default temperature and the controller starts a temperature conversion. The temperature register stores new temperature readings. The current temperature is loaded into the (user) temperature registers when a valid I2C slave address and write is received and when a word address is received. Consequently, if the two temperature registers are read in individual I2C transactions, it is possible for a temperature conversion to occur between reads, and the results can be inaccurate. To prevent this from occurring, the registers should be read using a single, multibyte read operation (Figure 5). I2C reads do not affect the internal temperature registers.
I2C Serial Data Bus
The DS4026 supports a bidirectional I2C bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data is defined as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS4026 operates as a slave on the I2C bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS4026 works in both modes. The following bus protocol has been defined (Figure 3): * Data transfer can be initiated only when the bus is not busy.
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 ACK START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 3. I2C Data Transfer Overview
10 ____________________________________________________________________
10MHz to 51.84MHz TCXO
* During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. Stop data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge (ACK) after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. Figures 4 and 5 detail how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge (ACK) bit after each received byte. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge (NACK) is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Because a repeated START condition is also the beginning of the next serial transfer, the bus is not released.
DS4026
ADDRESS> S 1000001 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
ADDRESS> S 1000001 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P DATA TRANSFERRED S = START (X + 1 BYTES + ACKNOWLEDGE) A = ACKNOWLEDGE NOTE: LAST DATA BYTE IS FOLLOWED BY P = STOP A NOT ACKNOWLEDGE (A) SIGNAL A = NOT ACKNOWLEDGE R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 83h
S = START DATA TRANSFERRED A = ACKNOWLEDGE (X + 1 BYTES + ACKNOWLEDGE) P = STOP R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 82h
Figure 4. Slave Receiver Mode (Write Mode) Figure 5. Slave Transmitter Mode (Read Mode)

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11
10MHz to 51.84MHz TCXO
The DS4026 can operate in the following two modes: Slave receiver mode (write mode): Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS4026 address, which is 1000001, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte, the DS4026 outputs an acknowledge on SDA. After the DS4026 acknowledges the slave address and write bit, the master transmits a word address to the DS4026. This sets the register pointer on the DS4026, with the DS4026 acknowledging the transfer. The master can then transmit zero or more bytes of data, with the DS4026 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. Slave transmitter mode (read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS4026 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS4026 address, which is 1000001, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address byte, the DS4026 outputs an acknowledge on SDA. The DS4026 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The DS4026 must receive a not acknowledge to end a read.
DS4026
Ordering Information (continued)
PART DS4026S+MCC DS4026S+MCN DS4026S+PCC DS4026S+PCN DS4026S+QCC DS4026S+QCN DS4026S+ACC DS4026S+ACN DS4026S+FCC DS4026S+FCN DS4026S+ECC DS4026S+ECN DS4026S+RCC DS4026S+RCN TEMP RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C OUTPUT (fNOM) (MHz, CMOS) 38.88 38.88 40.0 40.0 51.84 51.84 10.0 10.0 16.384 16.384 16.8 16.8 24.0 24.0 PIN-PACKAGE 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO TOP MARK* DS4026-MCC DS4026-MCN DS4026-PCC DS4026-PCN DS4026-QCC DS4026-QCN DS4026-ACC DS4026-ACN DS4026-FCC DS4026-FCN DS4026-ECC DS4026-ECN DS4026-RCC DS4026-RCN
+Denotes a lead-free package. *The top mark will include a "+" for a lead-free/RoHS-compliant device.
12
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10MHz to 51.84MHz TCXO
Chip Information
TRANSISTOR COUNT: 77, 712 SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
PACKAGE TYPE 16-pin SO (300 mils) DOCUMENT NO. 56-G4009-001
DS4026
Revision History
Pages changed at Rev 1: 1-12
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.

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